Due to higher data rates we can expect a significant increase in bandwidth, but the capacity per stack will remain at 24 GB.
Riding on the rise of HBM2 (High Bandwidth Memory 2), JEDEC announced last month a new standard for chips, the “JESD235C“is named and is not much different from the previous norm; unlike some major changes to 12-Hi stacks a few years ago, it's now a more consolidated upgrade that focuses on improving performance.
The biggest change is the support for the two higher data rates, 2.8Gbps / pin and 3.2Gbps / pin, which represents an increase of about 33 percent in bandwidth. Slightly more practical, this means that the fastest full HBM2 stack reached 410 GB / s, which is not a bad result compared to the previous 307.2 GB / s, and as a result, the modern 4-stack (4096 for high-end processors that handle memory, the aggregate bandwidth will be at least 1.65 TB / s.
|Max. Bandwidth / pin||3.2 Gbps||2.4Gbps||2 Gbps|
|Max. Chip capacity||2 GB||1 GB|
|Max chip / stack||12||8|
|Max capacity / stack||24 GB||8 GB|
|Max. Bandwidth / stack||410 GB / s||307.2 GB / s||256 GB / s|
|Effective bus width (1 stack)||1024 bit|
|Stress||1.2 volts||It was 1.35|
It's all nice and good, but thanks to the update, even a single stack of HBM2 remains competitive on the (bandwidth) front, as the aggregated value of the 256-bit GDDR6 memory bus backed by 14Gbps chips is 448GB / s, at that particular 410 GB / s. Additionally, HBM2 is easier to scale to more stacks than GDDR6 for larger bus widths, so the advantage of topology in this regard over the discrete GDDR6 chips, as long as the data rate is on the table.
Not all the joy and happiness is because it also comes with a pro, which in this case is nothing more than cost and capacity; HBM2 will remain thanks to premium technology, partly due to the complications of using TSVs, and partly due to manufacturers' product segmentation, and this is not expected to change in the near future. The new standard has no effect on memory size, so the single-stack maximum is still at 24GB, culminating at 96GB in a four-stack configuration.
As a note, JEDEC is a bit backward in its efforts to control the size of the HBM2 chip stack, so there is no standard height for 12-Hi stacks, so it can be determined by the memory manufacturers themselves. Since the chips are still running at 1.2 volts, the tempo gain may be accompanied by some extra consumption if combined.
Finally, it looks like JEDEC is officially adopting the name “HBM2E”, but it is more of a gesture-worthy maneuver, as the formal version remains the simple “HBM2”. In their previous announcements, Samsung, SK Hynix, and other companies mistakenly referred to the memory as HBM2E (Samsung still does), so it's likely that we'll see alternating forms in the report in the coming days.